1. Field of the Invention
The present invention generally relates to the field of semiconductors and, in particular, is directed to a flip chip ball grid array package and a method of making the same that minimizes cost and manufacture time while enhancing heat-dissipating efficiency.
2. Discussion of Related Art
Semiconductors are materials that have characteristics of insulators and conductors. In today's technology, semiconductor materials have become extremely important as the basis for transistors, diodes, and other solid-state devices. The most commonly used semiconductor materials include germanium and silicon, but selenium and copper oxide, as well as other materials, also are used. When properly made, semiconductors will conduct electricity in one direction better than they will in the other direction. A semiconductor chip is a highly miniaturized integrated electronic circuit. In its purest form, a semiconductor chip is a collection of transistors. The circuitry of the chip is provided in a layered form on a semiconductor material.
Wire bond, when applied to semiconductor chip devices, completes a wire connection providing electrical continuity between the semiconductor chip and a terminal. The constituents of an electrical connection may include any one or more of a fine metal wire, metal bonding surfaces (like a die pad), metallurgical interfaces underneath a bonded wire deformation, underlying insulating layer (if present), and a base layer element. Wire bonding is a method used to attach very fine metal wire to semiconductor components in order to interconnect the components with each other or with package leads. One problem encountered with wire bonds is the parasitic inductance that arises, which is based on the size and length of the wire carrying electricity to the components. Also, wire bonds are fragile and have limited current carrying capability.
A flip chip is a leadless monolithic structure, containing circuit elements, which is designed to electrically and mechanically connect to a hybrid circuit. Such connection may be, but is not limited to, a structure such as a number of bumps, which are covered with a conductive bonding agent and are formed on its front-side planar face. In one conventional flip chip mounting technique for integrated circuits, a semiconductor chip is placed front face-down on a mounting base layer element and is connected to wire patterns on the base layer element using the bumps as electrical contacts and the conductive bonding agent as an adhesive. Because the flip chip mounting technique can bond a chip to a base layer element over a much shorter distance than wire bonding, the effect of parasitic inductance can be reduced. Also, the thicker bumps are less fragile than wires and can conduct greater amounts of current. Some flip chips can thus be mounted onto a circuit base layer element with limited or even no need for wire bonding. Flip-chip mounting is thus drawing increasing interest as a mounting technique for high-frequency integrated circuits.
Emerging electronic product applications are creating a set of challenges for the integrated circuit (IC) packaging industry. With ever increasing requirements for greater functionality and lower system costs, a primary requirement for new packaging technology is low cost. Because of these cost requirements, the thermal, electrical, mechanical, and assembly characteristics of each IC package design must be optimally tailored, and not overdesigned. Characterization equipment and design tools for analyzing electrical, mechanical, and thermal performance are being used to enhance the package design, so that development cycle times are reduced, and cost targets are met. One such enhanced package design is the ball grid array (BGA), which can be used in flip chip applications.
BGA packages present numerous benefits previously unobtainable with the use of single packaging technology. BGAs provide higher pin counts over a smaller area and a robust “ball” structure that integrates seamlessly into the manufacturing process. Plastic Ball Grid Array (PBGA) packages are designed to provide low inductance, improved thermal operation and enhanced surface mount technology (SMT) capability. PBGA packages are ideal for use with specific integrated circuits (ASICs), microprocessors, controllers, gate arrays, memory, digital signal processors (DSPs) and personal computer (PC) chip set applications. PBGA packages are often coupled with flip chip designs.
The BGA package format presents challenges not encountered in the modeling of standard leaded packages due to the existence of more complex heat flow paths. For example, the conventional PBGA designs are not able to deliver the thermal performance that is possible with other package designs. Accordingly, the inability to remove heat generated during chip operation in conventional flip chip PBGA design has presented certain electrical and reliability disadvantages, as heat can often only be removed through the base layer element. A newer, enhanced BGA packaging technology is capable of providing a light-weight and very low profile high I/O packaging solution capable of superior thermal performance. In particular, high thermal performance is achieved through the use of a heat-spreader, which preferably is made of copper or AlSiC and is directly attached to the back face of the IC chip. Typically, the heat spreader must have a size larger than the surface of the die, in order to effectively distribute and dissipate heat generated by the die.
Examples of such conventional spreader-based flip chip PBGA design are illustrated in FIGS. 1A and 1B. The conventional high-performance flip chip plastic ball grid array package 100A, as illustrated in FIG. 1A, includes an organic base layer element 102. The base layer element 102 has a plurality of (preferably eutectic) solder balls 101 provided on the first surface 102a of the base layer element 102 for mounting to a circuit (not shown), and a flip chip die 103 mounted on the second surface 102b of the base layer element 102. The flip chip die 103 has conventional flip chip solder bumps 104 arrayed on the first surface 103a of the flip chip die 103 for coupling to conductive patterning (not shown) formed on the base layer element. An underfill epoxy 114 is applied about the sides 103c of the flip chip die 103, in order to secure the die to the base layer element 102 and to prevent damage to the solder bumps 104. The package 100A utilizes a metallic heat spreader 106 comprising two pieces, a first planar piece 106a, which is coupled by a thermal grease 109 to the second surface 103b of the flip chip die 103, and a second ring-shaped piece 106b, which serves to add strength to the structure. The second ring-shaped piece 106b is positioned around the flip chip die 103 in order to increase rigidity of the flip chip packaging assembly so that the first planar piece 106a of the metallic heat spreader 106 is adequately supported and so that the base layer element 102 will not warp during the various fabrication processes or during operation. An epoxy material 107, which ordinarily is non-conductive, is used to secure the second ring shaped piece 106b of the metallic heat spreader 106 to the base layer element 102 and to the first planar piece 106a of the metallic heat spreader 106. A disadvantage in the production of this design is that separate steps for application of the thermal grease 109 and epoxy material 107 are required, thus adding to the cost and potentially reducing the yield. U.S. Pat. No. 5,949,137 to Domadia et al. discloses a flip chip packaging assembly with a second ring-shaped piece 106b such as described.
The heat spreader may also be designed as a one-piece structure 108 for a chip package 100B, as illustrated in FIG. 1B. In the two-piece embodiment, the second ring shaped piece 106b is first secured to the base layer element 102, and then the first planar piece 106a is secured to the package. In the one-piece embodiment of FIG. 1B, a one piece heat spreader 108 having an integral structure comprising a planar part 108a and a peripheral supporting part 108b is affixed over the flip chip die 103. As in the embodiment of FIG. 1A, a thermal grease 109, which facilitates heat transfer, is applied between the planar part 108a of the one piece metallic heat spreader 108 and the second surface 103b of the flip chip die 103. An epoxy material 107 is applied to bond the peripheral supporting part 108b of the one piece metallic heat spreader 108 to the second surface 102b of the base layer element 102. Again, a disadvantage is that separate steps for application of the thermal grease 109 and epoxy material 107 are required.
In both prior art designs, as illustrated in FIGS. 1A and 1B, a space 115 is left between the second ring shaped piece 106b of the metallic heat spreader 106 or the peripheral supporting part 108b of the metallic heat spreader 108 and the underfill epoxy 114. The space is bounded by the second surface 102b of the base layer element 102 and the underside of the first planar piece 106a of the metallic heat spreader 106 or the planar part 108a of the metallic heat spreader 108, that overhangs the flip chip die 103.
Due to the structure of the conventional heat spreader designs illustrated in FIGS. 1A and 1B, the cost of fabrication is very high. For the two-piece design of FIG. 1A, two separate toolings are needed and at least two assembly steps are required to attach the metallic heat spreader 106 over the flip chip die 103. The second ring shaped piece 106b of the heat spreader 106 and the supporting part 108b of the heat spreader 108 reduce the area available for the mounting of semiconductor dies and/or other components within. The one-piece design of FIG. 1B requires special processes such as special powder injection molding or precision machining to produce the complex one-piece design.
Tight process control requirements are another disadvantage of the conventional BGA package with a metallic heat spreader. For example, with regard to the two-piece design of FIG. 1A, in order to mechanically bond the ring shaped piece 106b of the heat spreader 106 to the packaging base layer element 102, a thin bond layer of epoxy material 107 is applied between the ring shaped piece 106b and the packaging base layer element 102, and between the ring shaped piece 106b and the first planar piece 106a of the metallic heat spreader 106. A thermal grease 109 is applied between the flip chip die 103 and the planar piece 106a. Tight process control is required when dispensing the epoxy material 107 or thermal grease 109 during the assembly of the conventional package. This is because the die thickness and the heat spreader thickness are fixed, and a low profile is desired by design. Therefore the epoxy material 107 must be adequate to secure the heat spreader firmly to the flip chip die 103 and base layer element 102, yet not so thick as to increase the profile.
Accordingly, there is a need for an improved, economical flip chip package design that can overcome the above mentioned disadvantages with a low-cost heat spreader design that is easy to assemble and that provides comparable thermal characteristics.